元件例化语句实现4位全加器VHDL源程序
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY half_adder IS --一位半加器
PORT ( A,B : IN std_logic;
Co : OUT std_logic;
S : OUT std_logic);
END half_adder;
ARCHITECTURE rtl OF half_adder IS
SIGNAL tmp1,tmp2 : std_logic;
BEGIN
tmp1
tmp2
Co
S
END rtl;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OR_2 IS --或门
PORT(A,B:IN STD_LOGIC;
C:OUT STD_LOGIC);
END ENTITY OR_2;
ARCHITECTURE ART OF OR_2 IS
BEGIN
C
END ARCHITECTURE ART;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder IS --结构描述法设计一位全加器
PORT(A,B,Cin:IN STD_LOGIC;
S,Co:OUT STD_LOGIC);
END full_adder;
ARCHITECTURE structure OF full_adder IS
SIGNAL tmp1,tmp2,tmp3 : std_logic;
COMPONENT half_adder
PORT(A,B : IN std_logic;
Co : OUT std_logic;
S : OUT std_logic);
END COMPONENT;
COMPONENT OR_2
PORT(a,b : IN std_logic;
c : OUT std_logic);
END COMPONENT;
BEGIN
U0: half_adder
PORT MAP(A,B,tmp2,tmp1);
U1: half_adder
PORT MAP(tmp1,Cin,tmp3,S);
U2: OR_2
PORT MAP(tmp3,tmp2,Co);
END structure;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY full_adder_4 IS
PORT(X,Y:IN STD_LOGIC_VECTOR(1 TO 4);
C:IN STD_LOGIC;
SUM:OUT STD_LOGIC_VECTOR(1 TO 4);
CO:OUT STD_LOGIC);
END full_adder_4;
ARCHITECTURE struct OF full_adder_4 IS--结构描述法设计四位全加器 COMPONENT full_adder
PORT(A,B,Cin:IN STD_LOGIC;
S,CO:OUT STD_LOGIC);
END COMPONENT;
SIGNAL temp1,temp2,temp3,temp4:STD_LOGIC;
BEGIN
U1:full_adder PORT MAP(X(1),Y(1),C,SUM(1),temp1);
U2:full_adder PORT MAP(A=>X(2),B=>Y(2),Cin=>temp1,S=>SUM(2),Co=>temp2); U3:full_adder PORT MAP(A=>X(3),B=>Y(3),Cin=>temp2,S=>SUM(3),Co=>temp3); U4:full_adder PORT MAP(A=>X(4),B=>Y(4),Cin=>temp3,S=>SUM(4),Co=>temp4); CO
END struct;