数码管扫描显示控制器
数码管扫描显示控制器的设计与实现
姓名：
班级：2012211118
班内序号：
VHDL 程序
一． 实验中使用程序
1. 分频器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div IS
PORT(
clk:IN STD_LOGIC;
clear:IN STD_LOGIC;
clk_out:OUT STD_LOGIC);
END div;
ARCHITECTURE behav OF div IS
SIGNAL tmp:INTEGER RANGE 0 TO 49999;
BEGIN
p1:PROCESS(clear,clk)
BEGIN
IF clear='0' THEN
tmp
ELSIF clk'event AND clk='1' THEN
IF tmp=49999 THEN
tmp
ELSE
tmp
END IF;
END IF;
END PROCESS;
p2:PROCESS(tmp)
BEGIN
IF clk'event AND clk='1' THEN
IF tmp
clk_out
else
clk_out
END IF;
END IF;
END PROCESS p2;
END behav;
2. 数码管显示译码器（含计数器功能）：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY comp IS
PORT(
clk_in:IN STD_LOGIC;
cat:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
output:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END comp;
ARCHITECTURE behav OF comp IS
SIGNAL temp_cat:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL temp_out:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
PROCESS(clk_in)
BEGIN
IF(clk_in'EVENT AND clk_in='1')THEN
CASE temp_cat IS
WHEN"111110"=>temp_cattemp_cattemp_cattemp_cattemp_cattemp_cattemp_cat
END IF;
END PROCESS;
cat
output
END behav;
3. 数码管扫描显示控制器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SD6 IS
PORT(
CLK:IN STD_LOGIC;
CLEAR:IN STD_LOGIC;
CAT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
OUTPUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END SD6;
ARCHITECTURE behav OF SD6 IS
COMPONENT div
PORT(
clk:IN STD_LOGIC;
clear:IN STD_LOGIC;
clk_out:OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp
PORT(
clk_in:IN STD_LOGIC;
cat:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
output:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
SIGNAL temp_clk:STD_LOGIC;
BEGIN
u0:div PORT MAP(clk=>CLK,clk_out=>temp_clk,clear=>CLEAR); u1:comp PORT MAP(clk_in=>temp_clk,cat=>CAT,output=>OUTPUT); END behav;
二． 修改后程序
1. 分频器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div IS
PORT(
clk:IN STD_LOGIC;
clear:IN STD_LOGIC;
clk_out:OUT STD_LOGIC);
END div;
ARCHITECTURE behav OF div IS
SIGNAL tmp:INTEGER RANGE 0 TO 49999;
BEGIN
p1:PROCESS(clear,clk)
BEGIN
IF clear='0' THEN
tmp
ELSIF clk'event AND clk='1' THEN
IF tmp=49999 THEN
tmp
ELSE
tmp
END IF;
END IF;
END PROCESS;
p2:PROCESS(tmp)
BEGIN
IF clk'event AND clk='1' THEN
IF tmp
clk_out
else
clk_out
END IF;
END IF;
END PROCESS p2;
END behav;
2. 计数器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter IS
PORT(
clk_in:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END counter;
ARCHITECTURE behav OF counter IS
SIGNAL q_temp:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(clk_in)
BEGIN
IF(clk_in'event and clk_in='1')THEN
IF q_temp="101" THEN
q_temp
ELSE
q_temp
END IF;
END IF;
END PROCESS;
q
END behav;
3. 数码管显示译码器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY seg IS
PORT(a: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
led7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
cat: OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END seg;
ARCHITECTURE behav OF seg IS
BEGIN
PROCESS(a)
BEGIN
CASE a IS
WHEN "000"=>led7
WHEN "001"=>led7
WHEN "010"=>led7
WHEN "011"=>led7
WHEN "100"=>led7
WHEN "101"=>led7
WHEN OTHERS=>led7
END CASE;
END PROCESS;
END behav;
4. 数码管扫描显示控制器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISPLAY6 IS
PORT(
CLK:IN STD_LOGIC;
CLEAR:IN STD_LOGIC;
CAT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
OUTPUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END DISPLAY6;
ARCHITECTURE behav OF DISPLAY6 IS
COMPONENT div
PORT(
clk:IN STD_LOGIC;
clear:IN STD_LOGIC;
clk_out:OUT STD_LOGIC);
END COMPONENT;
COMPONENT counter
PORT(
clk_in:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT seg
PORT(
a: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
led7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
cat: OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
END COMPONENT;
SIGNAL temp_clk:STD_LOGIC;
SIGNAL temp_count:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
u0:div PORT MAP(clk=>CLK,clk_out=>temp_clk,clear=>CLEAR); u1:counter PORT MAP(clk_in=>temp_clk,q=>temp_count); u2:seg PORT MAP(a=>temp_count,led7=>OUTPUT,cat=>CAT); END behav;
仿真波形图（分频器为10分频器，与实验中使用分频器不同）