硬件电子琴电路设计
实验七 硬件电子琴电路设计
一．实验目的
学习利用蜂鸣器和按键设计硬件电子琴
二．实验内容
在MagicSOPC 试验箱上的实现一个简易的电子琴。按下KEY1-KEY7分别表
示中音的DO,RE,MI,FA,SOL,LA,S 按住KEY8再按KEY1-KEY7分别表示高音的DO,RE,MI,FA,SOL,LA,SI.
三. 实验原理
乐曲演奏原理：由于组成乐曲的每个音符的频率值（音调）及其持续时间（音
长）是乐曲演奏的2个基本数据，因此需要控制到扬声器的激励信号的频率高低和该频率信号持续的时间。
频率高低决定了音调的高低，而乐曲的简谱与各音名的频率对应关系如表1-1所列。
所有不同频率的信号都是从统一基准频率分频出来的。由于高阶频率多为非整数，而分频系数又不能为小数，故必须将计算所得的分频数进行四舍五入取整，并且其基准频率和分频系数应综合考虑加以选择，从而保证音乐不会走调。如在48MHZ 时钟下，中音1（对应的频率值是523.3Hz ）的分频系数应该为：
48000000/(2*523.3)=0xb327，这样需要对系统时钟进行45863次分频即可得到所要的中音1. 至于其他音符，同样可由一式求出对应的分频分数，这样利用程序可由轻松地得到相应的乐声。
本次实验是播放《友谊天长地久》，其乐谱如下：
四. 实验步骤
1．在QuartusII 中建立一个工程项目文件beep1.qpf, 并在该项目下新建Verilog HDL 源程 序文件beep1.v 输入程序代码并保存。 2．选择目标器件并不对相应的引脚进行锁定。
3．对 该工程文件进行全程编译处理，若在编译过程中发现错误，则找出并改正错误，直到编译成 功为止。
4．最后拿出跳线短接帽跳接jp7 和jp6,LED0-LED7,KEY1-KEY8,BEEP. 拿出下载电 缆，并对此电缆的两端分别接到PC 机的打印机并口和核心板上的JTAG 下载口上，打开电源， 执行下载命令，把程序下载到FPGA 器件中，现在按下键KEY1-KEY8 就可以开始使用电子琴 演奏音乐了。
五. 实验参考程序
//*********************************************************************// // 《友谊地久天长》乐曲 //
//
//
时钟：48MHz
//*********************************************************************// //音高与频率的对应关系
//---------------------------------------------------------------------- //|
|
1 | 2 | 3 | 4
|
5 | 6 | 7 |
//|低音 |261.6Hz |293.7Hz |329.6Hz |349.2Hz | 392Hz | 440Hz |493.9Hz | //|中音 |523.3Hz |587.3Hz |659.3Hz |698.5Hz | 784Hz | 880Hz |987.8Hz | //|高音 |1045.5Hz|1174.7Hz|1318.5Hz|1396.9Hz| 1568Hz | 1760Hz |1975.5Hz|
//---------------------------------------------------------------------- module song(clk,beep); input
clk;
//模块名称song
//系统时钟48MHz
//蜂鸣器输出端 //寄存器 //乐谱状态机
output beep; reg
beep_r;
reg[7:0] state;
reg[15:0]count,count_end; reg[23:0]count1;
//乐谱参数:D=F/2K (D:参数,F:时钟频率,K:音高频率) parameter L_5 = 16'd63776, //低音5
L_6 = 16'd56818, M_1 = 16'd47774, M_2 = 16'd42567, M_3 = 16'd37919,
//低音6 //中音1 //中音2 //中音3
M_5 = 16'd31888, M_6 = 16'd28409,
H_1 = 16'd23912;
parameter TIME = 12500000;
assign beep = beep_r;
always@(posedge clk) begin count
beep_r
end
end
always @(posedge clk) begin if(count1
count1 = count1 + 1'b1;
else begin
count1 = 24'd0;
//中音5 //中音6 //高音1
//控制每一个音的长短(250ms)
//输出音乐 //计数器加1
//计数器清零
//输出取反
//一个节拍250mS
if(state == 8'd147)
state = 8'd0;
else
state = state + 1'b1;
case(state)
8'd0,8'd1:
count_end = L_5;//低音"5", 持
续2个节拍
8'd2,8'd3,8'd4,8'd5,8'd6,8'd7,8'd8: count_end = M_1;//中音"1", 持续
7个节拍
8'd9,8'd10:
count_end = M_3;//中音"3", 持
续2个节拍
8'd11,8'd12,8'd13,8'd14: 8'd15:
count_end = M_2; count_end = M_1; count_end = M_2; count_end = M_3; count_end=M_1; count_end = M_3; count_end = M_5; count_end=M_6; count_end=M_6; count_end = M_5; count_end = M_3;
8'd16,8'd17: 8'd18,8'd19:
8'd20,8'd21,8'd22,8'd23,8'd24: 8'd25,8'd26: 8'd27,8'd28:
8'd29,8'd30,8'd31,8'd32,8'd33: 8'd34,8'd35,8'd36,8'd37,8'd38: 8'd39,8'd40,8'd41,8'd42: 8'd43,8'd44,8'd45:
8'd46,8'd47: count_end = M_1; count_end = M_2; count_end = M_1; count_end = M_2; 8'd48,8'd49,8'd50,8'd51: 8'd52:
8'd53,8'd54: 8'd55,8'd56:
8'd57,8'd58,8'd59,8'd60: 8'd61,8'd62,8'd63: 8'd64,8'd65:
8'd66,8'd67,8'd68,8'd69:
8'd70,8'd71,8'd72,8'd73: 8'd74,8'd75:
8'd76,8'd77,8'd78,8'd79: 8'd80,8'd81,8'd82: 8'd83,8'd84:
8'd85,8'd86,8'd87,8'd88: 8'd89:
8'd90,8'd91: 8'd92,8'd93:
8'd94,8'd95,8'd96,8'd97: 8'd98,8'd99,8'd100:
8'd101,8'd102:
count_end = M_3; count_end = M_1; count_end = L_6; count_end = M_5;
count_end = M_1; count_end = M_1;
count_end = M_6; count_end = M_5; count_end = M_3;
count_end = M_1; count_end = M_2; count_end = M_1; count_end = M_2; count_end = M_6; count_end = M_5;
count_end = M_3;
count_end = M_5;
8'd103,8'd104,8'd105,8'd106: 8'd107,8'd108,8'd109,8'd110: 8'd111,8'd112:
8'd113,8'd114,8'd115,8'd116: 8'd117,8'd118,8'd119: 8'd120,8'd121:
8'd122,8'd123,8'd124,8'd125: 8'd126:
8'd127,8'd128: 8'd129,8'd130:
8'd131,8'd132,8'd133,8'd134: 8'd135,8'd136,8'd137: 8'd138,8'd139:
8'd140,8'd141,8'd142,8'd143: 8'd144,8'd145,8'd146,8'd147:
default:count_end = 16'h0;
endcase
end
end endmodule
六. 编译仿真结果
count_end = M_6; count_end=M_6; count_end = H_1; count_end = M_5; count_end = M_3; count_end = M_1; count_end = M_2; count_end = M_1;
count_end = M_2; count_end = M_3; count_end = M_1; count_end = L_6; count_end = M_5; count_end = M_1; count_end = M_1;
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七. 体会思考
本次实验收获很多，通过这次试验我们熟悉了Verilog VHDL 语言的基本语法，形成了编写小系统的思路和方法。了解了简单音乐产生的原理，学会了分频器的灵活写法，熟悉了寄存器的使用，选择性开关的编写，并实践了两种不同的FPGA 中信息存储方式。通过本次实验掌握了如何用Verilog HDL语言实现硬件电子琴电路的原理，进一步掌握了课堂上所学到的知识，但同时充分的感觉到了自己的不足之处，今后一定要加强自己弱势方面的学习，用心学好EDA 教科书上的知识，并抽时间在课外进行深入地学习。
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