现代计算机组成原理--除法器设计
数字系统组成原理和设计技术
实验：除法器
学号 1115108052
姓名 詹炳鑫
班级 电子2班
华侨大学电子工程系
一．程序
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY devide IS
PORT
(
reset, clock, start : IN STD_LOGIC;
x : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
y : IN STD_LOGIC_VECTOR( 8 DOWNTO 0 );
done, overflow : OUT STD_LOGIC;
q, r : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 )
);
END devide;
ARCHITECTURE behav OF devide IS
SIGNAL rx : STD_LOGIC_VECTOR( 5 DOWNTO 0 );
SIGNAL ry : STD_LOGIC_VECTOR( 5 DOWNTO 0 );
SIGNAL rq : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL rmd : STD_LOGIC_VECTOR( 5 DOWNTO 0 );
SIGNAL flag_subadd : bit;
SIGNAL state : integer RANGE 0 TO 6;
BEGIN
PROCESS ( reset, clock )
V ARIABLE sq : STD_LOGIC;
BEGIN
IF reset = '0' THEN
rx '0' );
ry '0' );
rq '0' );
state
ELSIF clock'event AND clock = '1' THEN
CASE STATE IS
WHEN 0 =>
rx( 5 DOWNTO 0 )
ry( 5 DOWNTO 0 )
rq( 4 DOWNTO 0 )
flag_subadd
done
overflow
IF start = '1' THEN
state
END IF;
WHEN 1 =>
IF rmd(5) = '0' THEN
overflow
state
done
ELSE
state
sq := '0';
ry( 5 DOWNTO 0 )
rq( 4 DOWNTO 0 )
flag_subadd
END IF;
WHEN 5 =>
IF rmd(5) = '0' THEN
sq := '1';
flag_subadd
ELSE
sq := '0';
flag_subadd
END IF;
ry( 5 DOWNTO 0 )
ry( 5 DOWNTO 0 )
rq( 4 DOWNTO 0 )
state
WHEN 6 =>
IF rq(0) = '0' THEN
ry
r
ELSE
r
END IF;
state
q
done
WHEN OTHERS =>
IF rmd(5) = '0' THEN
sq := '1';
flag_subadd
ELSE
sq := '0';
flag_subadd
END IF;
ry( 5 DOWNTO 0 )
rq( 4 DOWNTO 0 )
state
END CASE;
END IF;
END PROCESS;
rmd
ry + NOT rx + 1;
END behav;
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "03/04/2014 15:45:59"
-- Vhdl Test Bench template for design : devide
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY devide_tb IS
END devide_tb;
ARCHITECTURE devide_arch OF devide_tb IS
-- constants
-- signals
SIGNAL clock : STD_LOGIC:='0';
SIGNAL done : STD_LOGIC:='0';
SIGNAL overflow : STD_LOGIC:='0';
SIGNAL q : STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";
SIGNAL r : STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";
SIGNAL reset : STD_LOGIC:='0';
SIGNAL start : STD_LOGIC:='0';
SIGNAL x : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR(8 DOWNTO 0);
CONSTANT CLK_P : TIME :=10 ns;
COMPONENT devide
PORT (
clock : IN STD_LOGIC;
done : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
reset : IN STD_LOGIC;
start : IN STD_LOGIC;
x : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1 : devide
PORT MAP (
-- list connections between master ports and signals
clock => clock,
done => done,
overflow => overflow,
q => q,
r => r,
reset => reset,
start => start,
x => x,
y => y
);
PROCESS BEGIN
CLOCK
W AIT FOR CLK_P;
CLOCK
W AIT FOR CLK_P;
END PROCESS;
reset
start
x
y
二．仿真图