EDA实验--元件例化语言描述的测频控制器
EDA 实验（三）
CLK 作是测频控制时钟频率固定为1HZ 。Fsin 是待测信号。
1、 1）、测频控制器工作功能仿真波形：
2）、测频控制器工作时序仿真波形：
2、1）、4位频率计工作功能仿真波形
4位频率计功能仿真分析：由功能仿真波形可以看出其低12位为[1**********]1，每四个一组转化后为105，经译码器后读得105。待测周期为9.52ms ，待测频率计算得105（1/0.00952）。输入数据与测得数据一致。
2）、4位频率计工作时序波形：
3、 1）、8位频率计工作功能仿真波形：
2）、8位频率计工作时序仿真波形：
8位频率计功能时序仿真分析：同理由时序仿真波形可以看出其低12位为[1**********]1，其于全部为0，每四个一组转化后为105，经译码器后读得105。其待测周期为9.52ms ，待测频率计算得105（1/0.00952）。输入数据与测得数据一致。且时序仿真波形与功能仿真波形相比出现了毛刺。
一、4位十进制计数器的VHDL 代码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port (clk,clr,ena:in std_logic;
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end cnt10;
architecture behav of cnt10 is
begin
process(clk,clr,ena)
variable cqi:std_logic_vector(3 downto 0);
begin
if clr='1' then cqi:=(others=>'0');
elsif clk'event and clk='0' then
if ena='1' then
if cqi
else cqi:=(others=>'0');
end if;
end if;
end if;
if cqi=9 then carry_out
else carry_out
cq
end process;
end behav;
二、4位锁存器VHDL 语言：
library ieee;
use ieee.std_logic_1164.all;
entity reg4b is
port(load : in std_logic;
din : in std_logic_vector(3 downto 0);
dout: out std_logic_vector(3 downto 0));
end;
architecture art of reg4b is
begin
process(load,din)
begin
if(load'event and load = '1')then
dout
end if;
end process;
end art;
三、测频控制器的VHDL 语言：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity testctl is
port( clk : std_logic;
tsten,clr_cnt,load : out std_logic);
end;
architecture art of testctl is
signal clk_div2 : std_logic;
begin
load
tsten
p1:process(clk)
begin
if clk'event and clk='1' then
clk_div2
end if;
end process;
p2:process(clk,clk_div2)
begin
if clk='0'and clk_div2='0' then
clr_cnt
else
clr_cnt
end if;
end process;
end art;
四、4位十进制频率计的顶层文件：
library ieee;
use ieee.std_logic_1164.all;
entity cui4 is
port(fsin,clk:in std_logic;
dout:out std_logic_vector(16 downto 0));
end;
architecture art of cui4 is
component cnt10
port( clk,clr,ena:in std_logic;
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end component;
component reg4b
port (load:in std_logic;
din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(3 downto 0));
end component;
component testctl
port ( clk:in std_logic;
tsten,clr_cnt,load:out std_logic);
end component;
signal ena:std_logic;
signal clr:std_logic;
signal load:std_logic;
signal carry0:std_logic;
signal carry1:std_logic;
signal carry2:std_logic;
signal clr_cnt:std_logic;
signal tsten :std_logic;
signal a,b: std_logic;
signal cq0,cq1,cq2,cq3:std_logic_vector(3 downto 0);
begin
u0:testctl port map(clk=>clk,tsten=>a,clr_cnt=>b,load=>load);
u1:cnt10 port map(clk=>fsin,clr=>b,ena=>a,cq=>cq0,carry_out=>carry0); u2:reg4b port map(load,cq0,dout(3 downto 0));
u3:cnt10 port map(clk=>carry0,clr=>b,ena=>a,cq=>cq1,carry_out=>carry1);
u4:reg4b port map(load,cq1,dout(7 downto 4));
u5:cnt10 port map(clk=>carry1,clr=>b,ena=>a,cq=>cq2,carry_out=>carry2); u6:reg4b port map(load,cq2,dout(11 downto 8));
u7:cnt10 port map(clk=>carry2,clr=>b,ena=>a,cq=>cq3,carry_out=>dout(16)); u8:reg4b port map(load,cq3,dout(15 downto 12));
end art;
五、8位十进制频率计的顶层文件：
library ieee;
use ieee.std_logic_1164.all;
entity cui8 is
port(fsin,clk:in std_logic;
dout:out std_logic_vector(32 downto 0));
end;
architecture art of cui8 is
component cnt10
port( clk,clr,ena:in std_logic;
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end component;
component reg4b
port (load:in std_logic;
din:in std_logic_vector(3 downto 0);
dout:out std_logic_vector(3 downto 0));
end component;
component testctl
port ( clk:in std_logic;
tsten,clr_cnt,load:out std_logic);
end component;
signal ena:std_logic;
signal clr:std_logic;
signal load:std_logic;
signal carry0:std_logic;
signal carry1:std_logic;
signal carry2:std_logic;
signal carry3:std_logic;
signal carry4:std_logic;
signal carry5:std_logic;
signal carry6:std_logic;
signal clr_cnt:std_logic;
signal tsten :std_logic;
signal a,b: std_logic;
signal cq0,cq1,cq2,cq3,cq4,cq5,cq6,cq7:std_logic_vector(3 downto 0); begin
u0:testctl port map(clk=>clk,tsten=>a,clr_cnt=>b,load=>load);
u1:cnt10 port map(clk=>fsin,clr=>b,ena=>a,cq=>cq0,carry_out=>carry0); u2:reg4b port map(load,cq0,dout(3 downto 0));
u3:cnt10 port map(clk=>carry0,clr=>b,ena=>a,cq=>cq1,carry_out=>carry1); u4:reg4b port map(load,cq1,dout(7 downto 4));
u5:cnt10 port map(clk=>carry1,clr=>b,ena=>a,cq=>cq2,carry_out=>carry2); u6:reg4b port map(load,cq2,dout(11 downto 8));
u7:cnt10 port map(clk=>carry2,clr=>b,ena=>a,cq=>cq3,carry_out=>carry3); u8:reg4b port map(load,cq3,dout(15 downto 12));
u9:cnt10 port map(clk=>carry3,clr=>b,ena=>a,cq=>cq4,carry_out=>carry4); u10:reg4b port map(load,cq4,dout(19 downto 16));
u11:cnt10 port map(clk=>carry4,clr=>b,ena=>a,cq=>cq5,carry_out=>carry5); u12:reg4b port map(load,cq5,dout(23 downto 20));
u13:cnt10 port map(clk=>carry5,clr=>b,ena=>a,cq=>cq6,carry_out=>carry6); u14:reg4b port map(load,cq6,dout(27 downto 24));
u15:cnt10 port map(clk=>carry6,clr=>b,ena=>a,cq=>cq7,carry_out=>dout(32)); u16:reg4b port map(load,cq7,dout(31 downto 28));
end art;