2014[数字逻辑设计]期末考试-试题及参考解答(1)

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电子科技大学2013 -2014学年第 二 学期期 末 考试 A 卷

课程名称：_数字逻辑设计及应用__ 考试形式： 闭卷 考试日期： 20 14 年 07 月 10 日 考试时长：_120___分钟

课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 % 本试卷试题由___六__部分构成，共__8___页。

题号 得分

一

二

三

四

五

六

七

八

九

十

合计

1. A circuit with 10 flip-flops can store ( 10 ) bit binary numbers, that is, include ( 1024 或 210 ) states at most.

2. A 5-bit linear feedback shift-register (LFSR) counter with no self-correction can have ( 31 或 25-1 ) normal states.

3. A modulo-24 counter circuit needs ( 5 ) D filp-flops at least. A modulo-500 counter circuit needs ( 3 ) 4-bit counters of 74x163 at least.

4. If an 74x148 priority encoder has its 1, 3, 4, and 5 inputs at the active level, the active LOW binary output is ( 010 ) .

5. State/output table for a sequential circuit is shown as Table 1. X is input and Z n is output. Assume that the initial state is S 0, if the input sequence is X = 01110101, the output sequence should be ( 11001100 或110011000 ). 【可以确定的输出序列应该有9位】

n+1n 21

.

6. Transition/output table for a sequential circuit is shown in Table 2, X is input and Y is output, the sequential circuit is a modulus ( 3 ) up/down counter.

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7. A serial sequence generator by feedback shift registers 74x194 is shown in Figure 1, assume the initial state is Q 2Q 1Q 0 = 100, the feedback function LIN = Q2’Q1’ + Q2Q 0’, the output sequence in Q2 is ( 100110 循环输出 ).

Figure 1

8. When the input is 01100000 of an 8 bit DAC, the corresponding output voltage is 3.76V. The output voltage 28−1255

range for the DAC is ( 0 ~ 9.99 或 3. 76×6 或 )V. 【本题并未对误差范围进行要求，3. 76×5

962+2

一般可保留2位小数。由于考试时没有计算器，写出算式也可】

1. The output signal of ( A ) circuit is 1-out-of-M code.

A. binary decoder B. binary encoder

C. seven-segment decoder D. decade counter

2. An asynchronous counter differs from a synchronous in ( B ).

A. the number of states in its sequence B. the method of clocking C. the type of flip-flop used D. the value of the modulus 3. There are ( D ) unused states for an n-bit Jonson counter.

A. n B. 2n C. 2n -n D. 2n -2n

4. The capacity of a memory that has 12 bits address bus and can store 8 bits at each address is ( A ).

A. 32768 B. 8192 C. 20 D. 256

5. Consider the following 4×4 “two-dimensional arbiter” shown in Figure 2 with inputs R 0, 0,R 0, 1,R 0, 2,R 0, 3, R 1, 0,R 1, 1,R 1, 2,R 1, 3, · · · R3, 0,R 3, 1,R 3, 2,R 3, 3 (“requests”) and outputs G 0, 0,G 0, 1,G 0, 2,G 0, 3,

G 1, 0,G 1, 1,G 1, 2,G 1, 3, · · · G3, 0,G 3, 1,G 3, 2,G 3, 3 (“grants”). Wi, 0’s and N 0,j ’s are also inputs, and Ei, 4’s and

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S 4,j ’s are also outputs. Assume 1ns gate delay for all gates (i.e., 2-AND and INV). The longest delay in Fig. 2 (in ns) is ( B ).

A. 19 B. 21 C. 23

D. 25

Figure 2. 4 ×

4 two-dimensional arbiter.

Figure 3. Logic for rectangle box.

【提示：不要被上图的气势所吓倒。从Figure 3可知，每个小方盒的最大延迟是3个门，即3ns ； 从Figure 2可知，最长通路经过了7个小方盒，如图中蓝线所示，因此，此电路最大延迟为3×7 = 21ns 】

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III. Analyze the clocked synchronous state machine shown in Figure 4.

(15’)

(1) Write out the excitation equations, the state transition equations and the output equations of the circuit. (4’) (2) Fill out the transition/output table

(6’)

(3) Assume initial state is 000, draw the state transition /output diagram. Important: Only include reachable

states in the diagram

(3’)

(2’)

(4) With initial state = 000, what states, if any, are not reacheable? Please list the unreachable states.

I

(2) The transition /output table:

000 0

参考答案： 000 0 111 0

Figure 4

(1) The excitation equation :

111 0 000 0 111 1 011 0 000 0 011 0 000 0 011 0 000 0 011 0 000 1

The output equation : F = Q2·Q1·Q0，

D0 = D1 = I’·Q0 + I·Q0’, D2 = I’·Q0

The state equation :

Q0* = Q1* = D0 = D1 = I’·Q0 + I·Q0’, Q2* = D2 = I’·Q0

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(3) The sate transition /output diagram:

(4) With initial state = 000, the unreachable states are: 001, 010, 100, 101, 110

IV . Consider the following Mealy machine with initial state A . (“d” means don’t care.)

Q2Q1Q0 A B C D

(1) Please fill out the transition/output table . (8’) 参考答案：

(2) Fill-in K-Map of D2,D1,D0, and output F if realized with D flip-flops. 参考答案：

I = 0 I = 1 I = 0 I = 1C A D D

D C C B

0 1 1 d

d 1 0 1

(15’)

Assume the following state encoding:

State Q2Q1Q0 (3’)

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D2

D0

(3) Derive the minimum two-level logic for D2, D1, D0 and F. (4’) 参考答案：

D2 = I’·Q2’·Q1’ + I·Q2 + I·Q0 或 D2 = (I’+Q2+Q0) · (I+Q2’) · (I+Q1’)

D1 = I·Q2’·Q1’ + I’·Q2 + Q1·Q0’ 或 D1 = I·Q2’·Q0’ + I’·Q2 + Q1·Q0’ 或 D1 = Q0’·(I’+Q2’)·(I+Q2+Q1) D0 = I·Q1·Q0’

F = I’·Q2 + Q1 或 F = (Q2+Q1) · (I’+Q2’) 或 F = (Q2+Q1) · (I’+Q1)

V . Consider the following sequential logic diagram in Figure 5. Assume the gate delay is 1 ns for

2-AND and 2ns for 2-XOR. Assume the positive edge-trigged flip-flop delay is TdelayFF = 1 ns, and Assume the positive edge-trigged flip-flop setup time is also TsetupFF = 1 ns.

Fill out the rest of the timing diagram for B , C , D , and Q. (15’)

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Figure 5

参考答案：

Figure 4

VI. 74X163 is a synchronous 4-bit binary counter with synchronous load and synchronous clear

inputs, the basic function table is shown as follow. Design a modulo-13 counter, using one 74X163 and some necessary gates, with the following counting sequence: 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 1, 2, …. (15’)

(1) Fill in the following K-Maps of LD_L, D, C, B, A with minimum cost. (6’) (2) Derive the minimum two-level logic expressions for LD_L, D, C, B, A. (6’) (3) Draw the logic diagram of this counter. (3’)

参考答案： (1)

(2) LD_L = QA’ + QC’·QD+ QC·QD’ + QB’·QD’

或LD_L = QA’ + QC’·QD+ QC·QD’ + QB’·QC’ 或LD_L = (QA’+QC’+QD’) · (QA’+QB’+QC+QD)

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D = QB’

C = QB’ + QD’ 或 C = QB’ + QC’ B = QB’

A = 1 或 A = QA

(3) 从成本和效率考虑，可将函数表达式尽量写成与非-与非式，即

LD_L = (QA·QC·QD)’ · (QA·QB·QC’·QD’)’ C = (QB·QD)’

+5V